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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75116H,75117H
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75117H is a 75X Series 4-bit single-chip microcomputer. The PD75117H is a product which has the same functions as those of the PD751xxF, with the minimum operating voltage reduced from the previous 2.7 V to 1.8 V, and achieving 1.91 s operation at 1.8 V. Therefore, it facilitates low-voltage operation for a set requiring high-speed operation. Functions are described in detail in the following User's Manual, which should be read when carrying out design work.
PD75117H User's Manual : IEU-799
FEATURES
* Memory capacity ROM : 24448 x 8 bits (PD75117H) : 16256 x 8 bits (PD75116H) RAM : 768 x 4 bits * High-speed low voltage operation Minimum instruction execution time : * Operating voltage range * Input/output ports : 58 * Timer/counter : 3 channels * Timer/event counter x 2 channels * Basic interval timer x 1 channel * 8-bit serial interface on chip * Programmable threshold port * On-chip PROM product available :
1.91 s (VDD = 1.8 V) 0.95 s (VDD = 2.7 V) 1.8 to 5.5 V (Ta = -40 to +60 C)
5
: :
4-bit resolution x 4 channels PD75P117H (One-time PROM)
APPLICATIONS
Cordless telephone subsets, portable radio equipment, pager, etc.
"Unless there are any particular functional differences, the PD75117H is described in this document as a representative product."
The information in this document is subject to change without notice.
Document No. IC-3120 (O.D.No. IC-8502) Date Published May 1994P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1994
PD75116H,75117H
ORDERING INFORMATION
Ordering Code Package 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic QFP QFP QFP QFP ( ( ( ( 14 12 14 12 mm) mm) mm) mm) Quality Grade Standard Standard Standard Standard
PD75116HGC-xxx-AB8 PD75116HGK-xxx-8A8 PD75117HGC-xxx-AB8 PD75117HGK-xxx-8A8
Remarks xxx: ROM code number
OVERVIEW OF FUNCTIONS
Item Basic instructions Instruction cycle ROM On-chip memory RAM General register 768 x 4 bits 4 bits x 8 x 4 banks (memory mapping) Total 58 * CMOS input pins * CMOS input/output pins 43 0.95 s, 1.91 s, 15.3 s (4.19 MHz operation) 3-stage switching capability 24448 x 8 bits (PD75117H), 16256 x 8 bits (PD75116H) Contents
Input/output port
: 10 : 32 (pins with LED direct drive capability*1) * N-ch open-drain input/output pins : 12 (pins with LED direct drive capability*2) (A pull-up resistor can be incorporated bit-wise.) * Comparator input pins (4-bit precision) : 4 * 8-bit timer/event counter x 2 * 8-bit basic interval timer (watchdog timer applicable) * 8 bits * LSB-first/MSB-first switchable * 2 transfer modes (transmission/reception and dedicated reception modes) * External : * Internal : * External : 3 4 2
Timer/counter
Serial interface
Vectored interrupt Test input Standby
* STOP/HALT mode * * * * Various bit manipulation instructions (set, reset, test, Boolean operation) 8-bit data transfer, comparison, operation, increment/decrement instructions 1-byte relative branch instruction GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte
Instruction set
Others
* Bit manipulation memory (bit sequential buffer: 16 bits) on chip * 64-pin plastic QFP ( 14 mm) * 64-pin plastic QFP ( 12 mm)
5
Package
5 * 1. When VDD = 5 V, IOL = 15 mA. 5 2. When VDD = 5 V, IOL = 10 mA.
2
PD75116H,75117H
DIFFERENCES BETWEEN PD75116H AND PD75117H
Item ROM
5
PD75117H
PD75116H
16256 x 8 bits (Mask ROM) 768 x 4 bits SBS register No Memory bank 0 2-byte stack 3 machine cycles 2 machine cycles
24448 x 8 bits (Mask ROM)
RAM
Stack Stack area Stack operation when subroutine call instruction is executed CALL instruction machine cycle CALLF instruction machine cycle BRA instruction CALLA instruction MOVT XA, BCDE MOVT XA, BCXA BR BCDE BR BCXA
Yes Memory banks 0, 1, 2 3-byte stack 4 machine cycles 3 machine cycles
Undefined operation
Normal operation
3
PD75116H,75117H
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ...................................................................................................... BLOCK DIAGRAM ................................................................................................................................... PIN FUNCTIONS .....................................................................................................................................
3.1 3.2 3.3 3.4
6 8 9
PORT PINS ....................................................................................................................................................... 9 OTHER PINS ..................................................................................................................................................... 10 PIN INPUT/OUTPUT CIRCUITS ..................................................................................................................... 11 RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................... 12
4. 5.
MEMORY CONFIGURATION ................................................................................................................. 13 PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 18
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PORT ................................................................................................................................................................. 18 CLOCK GENERATOR ....................................................................................................................................... 19 CLOCK OUTPUT CIRCUIT ............................................................................................................................... 20 BASIC INTERVAL TIMER ................................................................................................................................ TIMER/EVENT COUNTER ............................................................................................................................... SERIAL INTERFACE ......................................................................................................................................... PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .............................................................. 21 21 23 25
BIT SEQUENTIAL BUFFER ............................................................................................................................. 26
6. 7. 8. 9.
INTERRUPT FUNCTION ........................................................................................................................ 27 STANDBY FUNCTION ............................................................................................................................ 29 RESET FUNCTION .................................................................................................................................. 30 INSTRUCTION SET ................................................................................................................................. 33
10. APPLICATION EXAMPLE ....................................................................................................................... 43
10.1 CORDLESS TELEPHONE (SUBSET) .............................................................................................................. 43 10.2 DISPLAY PAGER .............................................................................................................................................. 44
11. MASK OPTION SELECTION ................................................................................................................... 45 12. ELECTRICAL SPECIFICATIONS ............................................................................................................. 46 13. PACKAGE INFORMATION ..................................................................................................................... 57 14. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 59 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD751xx SERIES PRODUCTS ......................... 60
4
PD75116H,75117H
APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................ 62 APPENDIX C. RELATED DOCUMENTS ........................................................................................................ 63
5
PD75116H,75117H
1. PIN CONFIGURATION (TOP VIEW)
RESET
P70
P71
P72
P73
P60
P61
P62
P63
P50
P51
P52
P53
50
64 P83 P82 P81 P80 P93 P92 P91 P90 VSS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 1 2 3 4 5
63
62
61
60
59
58
57
56
55
54
53
52
51
49 48 47 46 45 44
P40
X1
X2
P41 P42 P43 P30 P31 P32 P33 VDD IC* P140 P141 P142 P143 P130 P131 P132
PD75116HGC-xxx-AB8 PD75116HGK-xxx-8A8 PD75117HGC-xxx-AB8 PD75117HGK-xxx-8A8
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
43 42 41 40 39 38 37 36 35 34
24
25
26
27
28
29
30
31
33 32
P22/PCL
P21/PTO1
P20/PTO0
P02/SO
PTH00
TI0
TI1
P23
P03/SI
P01/SCK
P00/INT4
P123
P122
P121
P120
*
Connect the IC (Internally Connected ) pin to VDD directly.
6
P133
PD75116H,75117H
Pin Name P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 P120-P123 P130-P133 P140-P143 TI0, TI1 PTO0, PTO1 : : : : : : : : : : : : : : : Port 0 Port Port Port Port Port Port Port Port Port Port Port Port 1 2 3 4 5 6 7 8 9 12 13 14 PCL SCK SO SI PTH00-PTH03 : : : : : Programmable Clock Output Serial Clock Serial Data Output Serial Data Input Programmable Treshold Input External Vectored Interrupt Input 0, 1, 4 External Test Input 2, 3 System Clock Oscillation 1, 2 Reset Positive Power Supply Ground Internally Connected
INT0, INT1, INT4 : INT2, INT3 : X1, X2 : RESET : VDD VSS IC : : :
Timer Input 0, 1 Programmable Timer Output 0, 1
7
8
BASIC INTERVAL TIMER INTBT TI0 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE PROGRAM COUNTER (15) *1 ALU SP(8) CY SBS(2) *2 PORT 1 BANK PORT 2 PORT 3 ROM PROGRAM MEMORY 16256 x 8 BITS : PD75116H 24448 x 8 BITS : PD75117H GENERAL REG. PORT 4 DECODE AND CONTROL 4 4 P40-P43 4 4 P20-P23 4 P10-P13 BIT SEQ. BUFFER (16) PORT 0 4 P00-P03 P30-P33 PORT 5 RAM DATA MEMORY 768 x 4 BITS PORT 6 PORT 7 INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 INTERRUPT CONTROL fX / 2 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL CLOCK DIVIDER
N
2. BLOCK DIAGRAM
P50-P53 P60-P63
4 4
INTSIO
P70-P73
PORT 8
4
P80-P83
PORT 9
4
P90-P93
PTH00-PTH03
4
CLOCK GENERATOR
STAND BY CONTROL
PORT 12 CPU CLOCK PORT 13
4
P120-P123
PD75116H,75117H
4
P130-P133
PCL/P22
X1
X2 VDD VSS RESET PORT 14 4 P140-P143
* 1. The PD75116H program counter is composed of 14 bits. 2. The PD75117H incorporates the SBS register.
PD75116H,75117H
3. PIN FUNCTIONS
3.1 PORT PINS
Pin Name P00 P01 P02 P03 P10 P11
Input/Output Input Input/output Input/output Input
DualFunction Pin INT4 SCK
Function
8-bit I/O
Reset
I/O Circuit Type *1 B F
4-bit input port (PORT 0). SO SI INT0 INT1 Input P12 P13 P20 P21 Input/output P22 P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to P83 P90 to P93 Input/output Input/output Input/output Input/output Input/output Input/output Input/output PCL -- -- *2 Programmable 4-bit input/output port (PORT 3). Input/output can be specified bit-wise. *2 4-bit input/output port (PORT 4). 4-bit input/output port (PORT 5). *2 *2 INT2 INT3 PTO0 PTO1 4-bit input/output port (PORT 2). x 4-bit input port (PORT 1). x
Input E B
Input
B
Input
E
Input Input Input Input Input Input Input
E E E E E E E
-- -- --
Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise. *2 4-bit input/output port (PORT 7). 4-bit input/output port (PORT 8). 4-bit input/output port (PORT 9). *2 *2 *2
-- -- --
P120 to P123
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 12). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage *3 N-ch open-drain 4-bit input/output port (PORT 13). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage *3 N-ch open-drain 4-bit input/output port (PORT 14). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage *3
Input *4
M
P130 to P133
Input/output
--
Input *4
M
P140 to P143
Input/output
--
--
Input *4
M
* 1. : Schmitt trigger input 2. Direct LED drive capability (When VDD = 5 V, IOL = 15 mA). 3. Direct LED drive capability (When VDD = 5 V, IOL = 10 mA). 4. Open-drain ... high impedance On-chip pull-up resistor ... high level
5 5
9
PD75116H,75117H
3.2 OTHER PINS
Pin Name PTH00 to PTH03 TI0
Input/Output Input
DualFunction Pin --
Function Variable threshold voltage 4-bit analog input port. External event pulse input to timer/event counter. Or edge detection vectored interrupt input, or 1-bit input is also possible.
Reset
I/O Circuit Type *1 N
Input TI1 PTO0 Input/output PTO1 SCK SO SI Input/output Input/output Input
--
B
P20 Timer/event counter output. P21 P01 P02 P03 Serial clock input/output. Serial data output. Serial data input. Edge detection vector interrupt input (detection of both rising and falling edges) Input Input Input F E B Input E
INT4
Input
P00
Input
B
INT0 Input INT1 INT2 Input INT3 PCL Input/output
P10 P11 P12
Edge detection vector interrupt input (detection edge selectable)
Input
B
Edge detection test input (rising edge detection) P13 P22 Clock output System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. System reset input (low-level active). Internally Connected. IC pin should be connected to VDD directly. Positive power supply. GND potential.
Input
B
Input
E
X1, X2
Input
--
RESET IC VDD VSS
Input -- -- --
-- -- -- --
B
*
: Schmitt trigger input
10
PD75116H,75117H
3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75117H are shown by in abbreviated form. Fig. 3-1 Pin Input/Output Circuit List
Type A VDD data P-ch IN N-ch Type D output disable Type B IN/OUT Type F
CMOS standard input buffer Type B
This is an input/output circuit made up of a Type D push-pull output and Type B Schmitt-triggered input. Type M Pull-Up Resistor (Mask Option) N-ch (+6 V Withstand Voltage) VDD IN/OUT
data IN output disable
Schmitt-trigger input with hysteresis characteristic Type D VDD data P-ch OUT Type N
Middle-High Voltage Input Buffer (+6 V Withstand Voltage)
Comparator +
- output disable N-ch VREF (Threshold Voltage)
Push-pull output that can be made highimpedance output (P-ch and N-ch OFF) Type E
data Type D output disable
IN/OUT
Type A
This is an input/output circuit made up of a Type D push-pull output and Type A input buffer.
11
PD75116H,75117H
3.4 RECOMMENDED CONNECTION OF UNUSED PINS
Pin PTH00 to PTH03 TI0 TI1 P00 P01 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 Input status P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 IC Output status Connect to VSS.
Recommended Connection
Connect to VSS or VDD.
Connect to VSS or VDD. Connect to VSS.
: Connect to VSS or VDD.
: Leave open.
Connect to VDD directly.
12
PD75116H,75117H
4. MEMORY CONFIGURATION
* Program memory (ROM) : 24448 x 8 bits (0000H to 5F7FH) : PD75117H 16256 x 8 bits (0000H to 3F7FH) : PD75116H * 0000H, 0001H : Vector table in which a program start address after reset is written. * 0002H to 000BH : Vector table in which program start addresses after interruption are written. * 0020H to 007FH : Table area referred by GETI instruction
* Data memory * Data area : 768 x 4 bits (000H to 2FFH) * Peripheral hardware area : 128 x 4 bits (F80H to FFFH)
13
PD75116H,75117H
Fig. 4-1 Program Memory Map (1/2) (a) PD75117H
Address 7 0000H MBE 6 RBE 0 Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE RBE INT0/INT1 Start Address (High-Order 6 Bits) INT0/INT1 Start Address (Low-Order 8 Bits) 0006H MBE RBE INTSIO Start Address (High-Order 6 Bits) INTSIO Start Address (Low-Order 8 Bits) 0008H MBE RBE INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) 000AH MBE RBE INTT1 Start Address (High-Order 6 Bits) INTT1 Start Address (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address
BR !addr Instruction Branch Address BR BCDE BR BCXA Branch Address
0020H GETI Instruction Reference Table 007FH 0080H

CALL !addr Instruction Branch Address
Branch/Call Address by GETI
BRA !addr1 Instruction Branch Address

07FFH 0800H
CALLA !addr1 Instruction Branch Address
0FFFH 1000H
1FFFH 2000H
BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address
BR $addr1 Instruction Relative Branch Address (-15 to -1, +2 to +16)
2FFFH 3000H
3FFFH 4000H
4FFFH 5000H
5F7FH
Note
Since the above interrupt vector start address is a 14-bit address, set it in a 16K space (0000H to
3FFFH). Remarks Apart from the above instructions, branching is possible to an address at which only the PC loworder 8 bits have been changed by the BR PCDE or BR PCXA instruction.
14
PD75116H,75117H
Fig. 4-1 Program Memory Map (2/2) (b) PD75116H
Address 7 0000H MBE 6 RBE Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address INTBT/INT4 Start Address 0004H MBE RBE INT0/INT1 Start Address INT0/INT1 Start Address 0006H MBE RBE INTSIO Start Address INTSIO Start Address 0008H MBE RBE INTT0 Start Address INTT0 Start Address 000AH MBE RBE INTT1 Start Address INTT1 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address CALL ! addr Instruction Subroutine Entry Address 0
BR ! addr Instruction Branch Address
BR $ addr Instruction Relative Branch Address -15 to -1, +2 to +16
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
0FFFH 1000H
Branch Destination Address and Subroutine Entry Address by GETI Instruction BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address
1FFFH 2000H
2FFFH 3000H
3F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC loworder 8 bits have been changed by the BR PCDE or BR PCXA instruction.
15
PD75116H,75117H
Fig. 4-2 Data Memory Map (1/2) (a) PD75117H
Data Memory General Register Area 000H (32 x 4) 01FH 020H 256 x 4 0FFH 100H
Memory Bank
Bank 0
Data Area Static RAM (768 x 4)
256 x 4 Stack Area 1FFH 200H
Bank 1
256 x 4
Bank 2
2FFH Not On-Chip F80H Peripheral Hardware Area FFFH 128 x 4 Bank 15
16
PD75116H,75117H
Fig. 4-2 Data Memory Map (2/2) (b) PD75116H
Data Memory General Register Area Stack Area 000H (32 x 4) 01FH 020H 256 x 4 0FFH 100H
Memory Bank
Bank 0
Data Area Static RAM (768 x 4) 1FFH 200H
256 x 4
Bank 1
256 x 4
Bank 2
2FFH Not On-Chip F80H Peripheral Hardware Area FFFH 128 x 4 Bank 15
17
PD75116H,75117H
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORT
There are the following three digital input/output ports. * CMOS input (PORT0, PORT1) : 8
* CMOS input/output (PORT2 to PORT9) : 32 * N-ch open-drain input/output (PORT12 to PORT14) : 12 Total : 52
Table 5-1 Port Function
Port Name PORT 0
Function
Operation/Features
Remarks These pins are shared with SI, SO, SCK, INT0 to INT4.
4-bit input PORT 1 PORT 3 *1
Regardless of the operating mode of the shared pin, reading or test is always possible.
Can be set in the input or output bit-wise. PORT 6 *1 PORT 2 *1 PORT 4 *1 PORT 5 *1 PORT 7 *1 PORT 8 *1 PORT 9 *1 PORT12 *2 4-bit input/output PORT13 *2 PORT14 *2 (N-ch open-drain +6 V withstand voltage) Can be set to input or output mode as a 4-bit unit. Ports 12 and 13 are paired and data input/ output is possible as an 8-bit unit. On-chip pull-up resistor specifiable bit-wise by mask option.
4-bit input/output
Can be set in the input or output mode as a 4bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are paired and data input/output is possible as an 8-bit unit.
Port 2, PTO0, PTO1, and PCL share the same pins.
5 * 1. When VDD = 5 V, IOL = 15 mA. 5 2. When VDD = 5 V, IOL = 10 mA.
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PD75116H,75117H
5.2
CLOCK GENERATOR
The clock generator operation is determined by the processor clock control register (PCC). This circuit can also change the instruction execution time. * 0.95 s/1.91 s/15.3 s (4.19 MHz operation) Fig. 5-1 Clock Generator Block Diagram
* Basic Interval Timer (BT) * Clock Output Circuit * Timer/Event Counter * Serial Interface X1 1/8 to 1/4096 System Clock Oscillation Circuit X2
Selector
fXX or fX Frequency Divider 1/2 1/16
Oscillation Stop
Frequency Divider 1/4
* CPU * Clock Output Circuit
PCC PCC0
Internal Bus
PCC1 4 HALT * STOP * PCC2, PCC3 Clear PCC2 PCC3 R Q HALT F/F S
STOP F/F Q S
Wait Release Signal from BT
RESET Signal (Internal Reset) R Standby Release Signal from Interrupt Control Circuit
*
Instruction execution
1. 2. 3. 4. 5. fXX = Crystal/ceramic oscillator frequency fX = External clock frequency
Remarks
= CPU Clock
PCC : Processor clock control register One clock cycle (tCY) is one machine cycle. See "AC
CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for tCY.
5
19
PD75116H,75117H
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses to remote control outputs or peripheral LSI's. * Clock output (PCL) : , 524 kHz, 262 kHz (4.19 MHz operation) Fig. 5-2 Configuration of Clock Output Circuit
From Clock Generator
Output Buffer fXX/2
3
Selector PCL/P22
fXX/2
4
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 Output Latch
Bit 2 of PMGB Bit Specified in Port 2 Input/Output Mode
4 Internal Bus
20
PD75116H,75117H
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions. * It operates as an interval timer which generates reference time interrupts. * It can be applied as a watchdog timer which detects when a program is out of control. * Selects and counts wait times when the standby mode is released. * It reads count contents. Fig. 5-3 Basic Interval Timer Configuration
From Clock Generator fXX/2
5
Clear
Clear
fXX/2
7
MPX fXX/2 fXX/2
9
Basic Interval Timer (8-Bit Frequency Divider)
Set
BT Interrupt Request Flag
12
BT
IRQBT
Vector Interrupt Request Signal
3 Wait Release Signal during Standby Release
BTM3
BTM2
BTM1
BTM0
BTM
SET1*
4 Internal Bus
8
*
SET1 indicates instruction execution.
5.5 TIMER/EVENT COUNTER The PD75117H incorporates two internal timer/event counter channels. Timer/event counter channel 0 and channel 1 differ only in selectable count pulse (CP) and clock supply function to serial interface and are the same in other configurations and functions. * Operates as a programmable interval timer. * Outputs square waves in the desired frequency to the PTOn pin. * Operates as an event counter. * Use of TIn pin as an external interrupt input pin. * Divides the TIn pin input into N divisions and outputs it to the PTOn pin (frequency divider operation). * Supplies a serial shift clock to the serial interface circuit. (channel 0 only) * Count status read function.
21
22 Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
Internal Bus *1 SET1 8
TMn
8 8 Modulo Register (8) TOFn TMODn TOEn TO Enable Flag PORT2.n Bit 2 of PGMB TOn Port 2 P2n Input/ Output Output Latch Mode To Serial Interface (Channel 0 only) P2n/PTOn Output Buffer Edge Detector INTTn IRQTn Set Signal
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TIn
8 Comparator (8)
Match TOUT F/F TO Selector
Input Buffer TIn From Clock Generator MPX
8 Tn Count Register (8) CP Clear Timer Operation Start RESET
TMn1
TMn0
IRQTn Clear Signal
*
SET1 : Instruction execution.
PD75116H,75117H
PD75116H,75117H
5.6
SERIAL INTERFACE
The serial interface has the following functions. * Clock 8-bit transmission/reception operation (simultaneous transmission/reception) * Clock 8-bit reception operation (SO output high impedance) * Half-duplex asynchronous transfer (software control) * LSB-first/MSB-first switchable These functions facilitate serial bus data communications with other computers such as PD7500 series, 78K series, etc., or conjunction with a peripheral device.
23
24 Fig. 5-5 Serial Interface Block Diagram
Internal Bus 8 8 SIO0 P03/SI Shift Registor (8) SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 8 SET1 * SIOM P02/SO Serial Clock Counter (3) Overflow INTSIO IRQSIO Set Signal IRQSIO Clear Signal Clear P01/SCK R Q S fxx/2 MPX fxx/2
4
Serial Start
PD75116H,75117H
10
TOF0 (from Timer Channel 0)
* SET1 : instruction execution
PD75116H,75117H
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
The PD75117H is provided with 4-bit analog input pins (PTH00 to PTH03) for which the threshold voltage can be changed. These pins have a configuration as shown in Fig. 5-6. The threshold voltage (VREF) can be selected in 16 ways (VDD x ------ - VDD x ------) and analog signals can be 16 16 directly input. 7.5 This port can also be used as a digital signal input port by selecting VDD x ------ as VREF. 16 Fig. 5-6 Programmable Threshold Port Block Diagram
0.5 15.5
5
Input Buffer PTH00 + -
Programmable Threshold Port Input Latch (4)
PTH01
+ -
PTH02
+ -
PTH03
+
Internal Bus
-
Operation Stopped
PTH0
VDD PTHM7 1 2R R R MPX VREF PTHM4 8 PTHM3 1 2R 4 PTHM2 PTHM1 PTHM0 PTHM PTHM6 PTHM5
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PD75116H,75117H
5.8
BIT SEQUENTIAL BUFFER ****** 16 BITS
Bit manipulation of the bit sequential buffer is the bit manipulation special data memory. Since, in particular, the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient when processing data comprising a large number of bits bit-wise. Fig. 5-7 Bit Sequential Buffer Format
Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 BSB2 0 3 FC1H 2 1 0 3 FC0H 2 1 0
BSB3
BSB1
BSB0
L Register L = F
L=CL=B INCS L
L=8L=7 DECS L
L=4 L=3
L=0
Remarks
In pmem. @L addressing, the specified bit moves according to the L register.
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PD75116H,75117H
6. INTERRUPT FUNCTION
The PD75117H has 7 interrupt sources. Multiple interrupts with priority is are also possible. Two test sources are also provided. The test sources are edge detection testable inputs. Table 6-1 Interrupt Sources
Interrupt Source
Internal/External
Interrupt Order*1
Vector Interrupt Request Signal (Vector Table Address)
INTBT (standard time interval signal from basic interval timer) INT4 (both rising edge and falling edge detection) (rising edge and falling edge detection selection)
Internal 1 External External 2 External Internal 3 VRQ1 (0002H)
INT0 INT1
VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ5 (000AH)
INTSIO (serial data transfer end signal) INTT0 (match signal from timer/event counter# 0 or TI0 input edge detection) (match signal from timer/event counter# 1 or TI1 input edge detection)
Internal/external
4
INTT1
Internal/external
5
INT2*2 (rising edge detection) External INT3*2 (rising edge detection)
Testable input signal (Set IRQ2 and IRQ3)
*
1. The interrupt order is the priority order when multiple interrupt requests are generated simultaneously. 2. INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt sources, but do not generate vector interrupts. The PD75117H interrupt control circuit has the following functions: * Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Arbitrary setting of interrupt start address. * Multiple interruption function by which priority can be specified using the interrupt priority selection register (IPS). * Interrupt request flag (IRQxxx) test function (interrupt generation confirmation by software possible). * Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
27
28 Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus 2 IM1 2 IM0 9 Interrupt Enable Flag (IEXXX) (IME) 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11
Edge Detection Circuit Edge Detection Circuit Edge Detection Circuit
Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQT1 IRQ2 IRQ3 Interrupt Request Flag Standby Release Signal Priority Control Circuit Vector Table Address Generator
INTSIO INTT0 INTT1 INT2 /P12 INT3 /P13
Edge Detection Circuit Edge Detection Circuit
PD75116H,75117H
PD75116H,75117H
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the PD75117H has two standby modes (STOP mode and HALT mode). Table 7-1 Standby Mode Setting and Operation Status
STOP Mode Setting instruction Clock generator STOP instruction System clock oscillation stopped
HALT Mode HALT instruction Only CPU clock stopped Operable (IRQBT set at reference time intervals)
Basic interval timer
Operation stopped
Operation Status
Serial interface
Operation possible only when the external SCK input and TO0 output (when timer/event counter 0 is external TI0 input) are selected as a serial clock Operable only when TIn pin input specified as count clock Operation stopped Operation of INT0 to INT4 possible Operation stopped
Operation possible if a clock other than is specified as a serial clock
Timer/event counter
Operation possible
Clock output circuit External interrupt CPU
Except CPU clock , output possible.
Operation stopped
Release signal
Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input
29
PD75116H,75117H
8. RESET FUNCTION
The reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input
Wait (31.3 ms/4.19 MHz) RESET Input
Operating Mode or Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
The state of hardware after reset operation is as shown in Table 8-1.
30
PD75116H,75117H
Table 8-1 Status of Each Hardware after Resetting (1/2)
Hardware
RESET Input in Standby Mode Low-order 6 bits of program memory address 0000H are set in PC13 to PC8 and the contents of address 0001H are set in PC7 to PC0. PC14*1 is set to 0. Held 0 0
RESET Input during Operation Low-order 6 bits of program memory address 0000H are set in PC13 to PC8 and the contents of address 0001H are set in PC7 to PC0. PC14*1 is set to 0. Undefined 0 0
Program counter (PC)
Carry flag (CY) Skip flag (SK0 to SK2) PSW Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Sets program memory Sets program memory address 000H bit 6 and bit 7 address 000H bit 6 and bit 7 to RBE and MBE, to RBE and MBE, respecrespectively. tively. Undefined Undefined Held *2 Held 0, 0 Undefined 0 0 FFH 0 0, 0 Held 0 0 0 Undefined Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Undefined 0 0 0
Stack pointer (SP) Stack bank selection register (SBS) *1 Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Counter (BT) Mode register (BTM) Counter (Tn) Timer/event counter (n = 0, 1) Modulo register (TMODn) Mode register (TMn) TOEn, TOFn Shift register (SIO) Serial interface Mode register (SIOM) Clock generator, clock output circuit Processor clock control register (PCC) Clock output mode register (CLOM)
Basic interval timer
* 1. Compatible with the PD75117H only. 2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
31
PD75116H,75117H
Table 8-1 Status of Each Hardware after Resetting (2/2)
Hardware
RESET Input in Standby Mode IRQ1,IRQ2, IRQ4 Other than above Undefined 0 0 0 0, 0 OFF Clear (0) 0 Undefined 0 0
RESET Input during Operation Undefined 0 0 0 0, 0 OFF Clear (0) 0 Undefined 0 0
5
Interrupt request flag (IRQxxx) Interrupt function
Interrupt enable flag (IExxx) Priority selection register (IPS) INT0, INT1 mode registers (IM0, IM1) Output buffer
Digital port
Output latch I/O mode register (PMGA, PMGB, PMGC) PTH00 to PTH03 input latch
Analog port Mode register (PTHM) Bit sequential buffer (BSB0 to BSB3)
32
PD75116H,75117H
9.
INSTRUCTION SET
(1) Operand identifier and description The operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (For details, refer to RA75X Assembler Package User's Manual Language Volume (EEU-730).) When there are multiple elements in the description, one of the elements is selected. Upper case letters and symbols (+,-) are keywords and are described unchanged. Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (For details, refer to PD75117H User's Manual (IEU-799).) However, there are restrictions on the labels for which fmem and pmem can be used.
Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L
Description
XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
PD75116H PD75117H
0000H to 3F7FH immediate data or label 0000H to 3FFFH immediate data or label
0000H to 5F7FH immediate data or lebel 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT 0 to PORT 9, PORT12 to PORT14 IEBT, IESIO, IET0, IET1, IE0 to IE4 RB0 to RB3 MB0, MB1, MB2, MB15
*
In the case of the 8-bit data processing, an even address only can be described for mem.
33
PD75116H,75117H
(2) Operation description legend A : A register; 4-bit accumulator B : B register C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Extension register pair (XA') Extension register pair (BC') Extension register pair (DE') Extension register pair (HL') Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Portn (n = 0 to 9, 12 to 14) Interrupt master enable flag Interrupt priority selection register Interrupt enable flag Register bank selection register Memory bank selection register Processor clock control register Address, bit delimiter
: Contents addressed by xx : Hexadecimal data
34
PD75116H,75117H
(3) Description of addressing area field symbols
*1 *2 *3 MB = MBE * MBS (MBS = 0, 1, 2, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 0 : MB = MBS (MBS = 0, 1, 2, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3F7FH (PD75116H) 0000H to 3FFFH (PD75117H) *7 * PD75116H addr = (Current PC) -15 to (Current PC) -1, (Current PC) + 2 to (Current PC) + 16 * PD75117H addr1 = (Current PC) -15 to (Current PC) -1, (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H to 0FFFH (PC 13, 12 = 00B : PD75116H) = 0000H to 0FFFH (PC14, 13, 12 = 000B : PD75117H) = 1000H to 1FFFH (PC13, 12 = 01B : PD75116H) = 1000H to 1FFFH (PC14, 13, 12 = 001B : PD75117H) = 2000H to 2FFFH (PC13, 12 = 10B : PD75116H) = 2000H to 2FFFH (PC14, 13, 12 = 010B : PD75117H) = 3000H to 3F7FH (PC 13, 12 = 11B : PD75116H) = 3000H to 3FFFH (PC14, 13, 12 = 011B : PD75117H) = 4000H to 4FFFH (PC14, 13, 12 = 100B : PD75117H) = 5000H to 5F7FH (PC14, 13, 12 = 101B : PD75117H) *9 *10 *11 faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 0000H to 5F7FH ( : PD75117H only) Program memory addressing
Data memory addressing
*4
*5 *6
Remarks
1. 2. 3. 4.
MB indicates the accessible memory bank. For *2, MB = 0 without regard to MBE and MBS. For *4 and *5, MB = 15 without regard to MBE and MBS. *6 to *10 indicate the addressable area.
35

PD75116H,75117H
(4) Explanation of machine cycle field S shows the number of machine cycles required when skip is performed by an instruction with skip. The value of S changes as follows: * No skip ....................................................................................................................................................................... S = 0 * When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1 * When instruction to be skipped is 3-byte instruction .......................................................................................... S = 2 (BR !addr, BRA !addr1*, CALL !addr, CALLA !addr1* instructions) * This instruction is valid for the PD75117H only. One machine cycle is required to skip a GETI instruction.
Note
One machine cycle is equivalent to one cycle (= tCY) of the CPU clock. Three times can be selected by PCC setting.
36
PD75116H,75117H
Instruction Group
Mnemonic
Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HLA, @rpa1
Bytes Machine Cycles 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 A n4
Operation
Addressing Area
Skip Condition Stack A
reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8 + DE)ROM *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH Stack A Stack B
MOV
XA, @HL @HL, A @HL, XA A, mem XA, mem
Transfer
mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HLA, @rpa1 XCH XA, @HL A, mem XA, mem A,reg1 XA, rp' XA, @PCDE
XA (PC14-8 + DE)ROM XA (PC13-8 + XA)ROM XA (PC14-8 + XA)ROM XA (B2-0 + CDE)ROM XA (B2-0 + CXA)ROM *11 *11
XA, @PCXA Table reference MOVT XA, @BCDE* XA, @BCXA*
1 1 1
3
3 3
* The 3 lower bits in the B register are valid only. Remarks Shading indicates a part compatible with the PD75117H.
37
PD75116H,75117H
Instruction Group
Mnemonic
Operands CY, fmem.bit CY, pmem.@L
Bytes Machine Cycles 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
Operation CY (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit(L1-0)) CY (H + mem3 - 0.bit) (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit(L1-0)) CY (H + mem3 - 0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1, CY rp'1 - XA - CY A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
Addressing Area *4 *5 *1 *4 *5 *1
Skip Condition
Bit transfer
MOV1
CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY A, #n4 XA, #n8
carry carry *1 carry carry carry *1
ADDS
A, @HL XA, rp' rp'1, XA A, @HL
ADDC
XA, rp' rp'1, XA A, @HL
*1
borrow borrow borrow
SUBS
XA, rp' rp'1, XA A, @HL
*1
Operations
SUBC
XA, rp' rp'1, XA A, #n4
AND
A, @HL XA, rp' rp'1, XA A, #n4
*1
OR
A, @HL XA, rp' rp'1, XA A, #n4 A, @HL
*1
*1
XOR XA, rp' rp'1, XA
38
PD75116H,75117H
Instruction Group
Mnemonic A A
Operands
Bytes Machine Cycles 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S
Operation CY A0, A3 CY, An-1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear
Addressing Area
Skip Condition
Accumulator RORC manipulation NOT
reg rp1 INCS Increment /decrement @HL mem DECS reg rp' reg, #n4 @HL, #n4 Comparison SKE A, @HL XA, @HL A, reg XA, rp' SET1 Carry flag CLR1 manipulation SKT NOT1 CY CY CY CY mem.bit SET1 fmem.bit pmem.@L @H + mem.bit mem.bit fmem.bit CLR1 pmem.@L @H + mem.bit mem.bit Memory bit manipulation SKT fmem.bit pmem.@L @H + mem.bit mem.bit fmem.bit SKF pmem.@L @H + mem.bit fmem.bit SKTCLR pmem.@L
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
CY = 1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1 (pmem.@L) = 1
@H + mem.bit
2
2+S
*1
(@H + mem.bit) = 1
39
PD75116H,75117H
Instruction Group
Mnemonic
Operands CY, fmem.bit
Bytes Machine Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) PC13-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) PC14-0 addr1 (The assembler selects the optimum instruction from among the BR !addr, BRA !addr1, BRCB !caddr, and BR $addr1 instructions.) PC13-0 addr
Skip Addressing Condition Area *4 *5 *1 *4 *5 *1 *4 *5 *1
AND1
CY, pmem.@L CY, @H + mem.bit CY, fmem.bit
Memory bit manipulation
OR1
CY, pmem.@L CY, @H + mem.bit CY, fmem.bit
XOR1
CY, pmem.@L CY, @H + mem.bit
addr *1
--
--
*6
addr1
--
--
*11
BR
!addr $addr $addr1
3 1 1 2
3 2 2 3
*6
PC14-0, PC13-0 addr PC13-0 addr PC14-0 addr1 PC13-0 PC13-8 + DE *7
Branch PCDE
PC14-0 PC14-8 + DE PC13-0 PC13-8 + XA PC14-0 PC14-8 + XA
PCXA
2
3
BCDE *2 BCXA *2 BRA BRCB !addr1 !caddr
2 2 3 2
3 3 3 2
PC14-0 B2-0 + CDE PC14-0 B2-0 + CXA PC14-0 !addr1 PC13-0 PC13,12 + caddr11-0 PC14-0 PC14,13,12 + caddr11-0 (SP - 4) (SP - 1) (SP - 2) PC11-0
*11 *11 *11 *8
3 Subroutine stack control
(SP - 3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP-4 *6
CALL
!addr
3 4
(SP - 2) x, x, MBE, RBE (SP - 6) (SP - 3) (SP - 4) PC11-0 (SP - 5) 0, PC14, PC13, PC12 PC14 0, PC13-0 addr, SP SP-6
*
1. PD75116H only. 2. The 3 lower bits in the B register are valid only. Shading indicates a part compatible with the PD75117H.
Remarks 40
PD75116H,75117H
Instruction Group
Mnemonic
Operands Bytes Machine Cycles
Operation (SP - 2) x, x, MBE, RBE
Addressing Skip Condition Area
CALLA
!addr1
3
3
(SP - 6) (SP - 3) (SP - 4) PC11-0 (SP - 5) 0, PC14, PC13, PC12 PC14-0 addr1, SP SP-6 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, PC12 PC13-0 000 + faddr, SP SP - 4 (SP - 2) x, x, MBE, RBE
*11
2 CALLF !faddr 2 3
*9
(SP - 6) (SP - 3) (SP - 4) PC11-0 (SP - 5) 0, PC14, PC13, PC12 PC14-0 0000 + faddr, SP SP - 6 MBE, RBE, PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4
RET Subroutine stack control
1
3
PC11-0 (SP) (SP + 3) (SP + 2) x, PC14, PC13, PC12 (SP + 1) x, x, MBE, RBE (SP + 4) SP SP +6 MBE, RBE, PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4, then skip unconditionally
RETS
1
3+S
PC11-0 (SP) (SP + 3) (SP + 2) x, PC14, PC13, PC12 (SP + 1) x, x, MBE, RBE (SP + 4) SP SP +6 then skip unconditionally PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP +6
Unconditional
RETI
1
3
PC11-0 (SP) (SP + 3) (SP + 2) x, PC14, PC13, PC12 (SP + 1) PSW (SP + 4) (SP + 5), SP SP +6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0
rp PUSH BS rp POP BS EI Interrupt control DI IExxx IExxx
1 2 1 2 2 2 2 2
1 2 1 2 2 2 2 2
Remarks
Shading indicates a part compatible with the PD75117H.
41
PD75116H,75117H
Instruction Group
Mnemonic IN *1
Operands A, PORTn XA, PORTn
Bytes Machine Cycles 2 2 2 2 2 2 1 2 2 2 2 2 2 1 2 2 A PORTn
Operation (n = 0 to 9, 12 to 14)
Addressing Skip Condition Area
Input/output *1 OUT HALT CPU control STOP NOP SELL
XA PORTn + 1, PORTn (n = 4, 6, 8, 12) PORTn A (n = 2 to 9, 12 to 14)
PORTn, A PORTn, XA
PORTn + 1, PORTn XA (n = 4, 6, 8, 12) Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n (n = 0 to 3)
RBn MBn
2 2
MBS n (n = 0, 1, 2, 15)
* TBR Instruction PC13-0 (taddr)5-0 (taddr + 1) PC14 0 -----------------------------------------------------------------------* TCALL Instruction 3 1 (SP - 5) (SP - 6) (SP - 3)(SP - 4) PC14-0 (SP - 2) (x, x, MBE, RBE) PC13-0 (taddr)5-0 (taddr + 1) SP SP - 6 PC14 0 -----------------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed 3 at (taddr) and (taddr + 1) 4 * TBR Instruction PC13-0 (taddr)5-0 (taddr + 1) PC14 0 -----------------------------------------------------------------------* TCALL Instruction (SP - 5) (SP - 6) (SP - 3)(SP - 4) x, PC14-0 (SP - 2) x, x, MBE, RBE 4 PC13-0 (taddr)5-0 (taddr + 1) SP SP - 6, PC14 0 -----------------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed 3 at (taddr) and (taddr + 1) 3 *10
------------------------
Special
*2 GETI
taddr
-----------------------Conforms to referenced instruction.
-----------------------*10
1
----------------------Conforms to referenced instruction.
*
1. When executing the IN/OUT instruction, or must be set. 2. The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction. Shading indicates a part compatible with the PD75117H.
Remarks
42
10.1 CORDLESS TELEPHONE (SUBSET)
10. APPLICATION EXAMPLE
Power Amp IDC
Amp Compression Transmitter/ Receiver
MSK Modem Prescaler
MPX
Extension
Speaker VCO PLL TCXO MPX Prescaler LED Display Speaker Amp
PD7511H
VCO
PLL
Key Matrix
Radio Wave Detection
SIO
LCD Controller/ Driver
LED Display
Extra-Area Detection
PD7228 Console
ID ROM
PD6252
Detection
PD75116H,75117H
Mixer 2SC4226 3SK177
Filter
Amp 2SC2757 2SC4182
Legend IDC LED PLL VCO : : : : Immediate Deviation Controller, Light Emitting Diode, Phase Locked Loop, Voltage Control Oscillator ID ROM MPX SIO : : : ID (Identification) Code ROM, LCD Multiplexer Serial Data Input/Output MSK TCXO : : : Liquid Crystal Display Minimum Shift Keying Temperature Compensation Crystal Oscillator
43
PD75116H,75117H
10.2 DISPLAY PAGER
PD75117H
Filter
INT RAM
Code ROM Switch TO High-Current Output LED Display
Piezoelectric Buzzer
Comparator Input SIO LCD Controller/Driver PD7228/7229 LCD Display
Battery Check
44
PD75116H,75117H
11. MASK OPTION SELECTION
The PD75117H has the following mask option.
Pin Function Mask Option * Pull-up resistor (can be specified bit-wise.) * No pull-up resistor (can be specified bit-wise.)
P12 to P14
45
PD75116H,75117H
5
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Supply voltage SYMBOL VDD VI1 Input voltage VI2*1 Ports 12 to 14 Open-drain Output voltage Output current high VO One pin IOH All pins Peak value One pin Effective value Peak value Output current low IOL*2 Total of ports 0, 2, 12 to 14 Effective value Peak value Total of ports 3 to 9 Effective value Operating temperature Storage temperature Topt 60 -40 to +60 mA C C 60 100 mA mA 15 100 mA mA -30 30 mA mA -0.3 to +7.3 -0.3 to VDD +0.3 -15 V V mA Except ports 12, 13 and 14 Internal pull-up resistor TEST CONDITIONS RATING -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 UNIT V V V
Tstg
-65 to +150
*
1. When a voltage exceeding 6V is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor) should be 50K or more. 2. Effective value should be calculated: [Effective value] = [Peak value] x duty
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. The absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
OPERATING VOLTAGE RANGE
PARAMETER CPU Programmable threshold port (comparator input) Other hardware
TEST CONDITIONS
MIN. - 40 - 10 - 40
MAX. + 60 + 60 + 60
UNIT C C C
46
PD75116H,75117H
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance Input/output capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V 15 pF TEST CONDITIONS MIN. TYP. MAX. 15 15 UNIT pF pF
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = -40 to +60 C, VDD = 1.8 to 5.5 V)
RESONATOR RECOMMENDED CONSTANT PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
*1 Ceramic resonator C1
X1
X2
*2 Oscillator frequency (fXX) After VDD reaches MIN. of oscillation voltage range
2.0
5.0 *4
MHz
C2
*3 Oscillation stabilization time
4
ms
*1 Crystal resonator C1
X1
X2
*2 Oscillator frequency (fXX)
2.0
4.19
5.0 *4
MHz
C2
Oscillation *3 stabilization time
VDD = 4.5 to 5.5 V
10 30
ms ms
*5 External clock
X1
X2
X1 input *2 frequency (fX) VDD = 2.7 to 5.5 V X1 input high-/low-level width (tXH, tXL)
2.0
5.0 *4
MHz
PD74HCU04
100
250
ns
*
1. When using in VDD < 2.7 V, the X2 pin oscillation waveform duty should be set within the range between 40% and 60%.
Duty = tXXL (or tXXH) tXXL + tXXH VDD x 100
X2 Oscillation Waveform
1 VDD 2
VSS tXXL tXXH
2. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC CHARACTERISTICS for instruction execution time. 3. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of oscillation voltage range or the STOP mode is released. 4. When the oscillator frequency is 4.19 MHz < fXX 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s and the rated MIN. value of 0.95 s is not observed. 5. The external clock cannot be used in VDD < 2.7 V. 47
PD75116H,75117H
Note
When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. * A signal should be not taken from the oscillator.
RECOMMENDED OSCILLATION CIRCUIT CONSTANT RECOMMENDED CERAMIC RESONATOR (Ta = -40 to +60 C)
MANUFACTURER FREQUENCY (MHz) EXTERNAL CAPACITANCE (pF) C1 47 C2 47 OSCILLATION VOLTAGE RANGE [V] MIN. MAX.
PRODUCT NAME KBR-2.0MS PBRC 2.00A KBR-4.0MSA PBRC 4.00A KBR-4.0MKS KBR-4.0MWS
2.00
33 4.00 Iincorporated
33
Iincorporated
Kyocera
KBR-4.19MSA PBRC 4.19A KBR-4.19MKS KBR-4.19MWS KBR-5.0MSA PBRC 5.00A KBR-5.0MKS KBR-5.0MWS 5.00 4.19
33
33
1.8
5.5
Iincorporated
Iincorporated
33
33
Iincorporated
Iincorporated
48
PD75116H,75117H
DC CHARACTERISTICS (Ta = -40 to +60 C, VDD = 1.8 to 5.5 V)
PARAMETER SYMBOL TEST CONDITIONS Other than below Ports 0,1,TI0, 1, RESET Internal pull-up resistor N-ch open- drain VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VIL1 Input voltage low VIL2 VIL3 Other than below Ports 0,1,TI0, 1, RESET X1, X2 VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V IOH = -1 mA Output voltage high VOH IOH = -100 A VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V IOL = 15 mA Ports 0, 2, 4 to 8 IOL = 1.6 mA IOL = 400 A IOL = 100 A IOL = 15 mA IOL = 10 mA Output voltage low VOL Ports 3, 9 IOL = 1.6 mA IOL = 400 A IOL = 100 A IOL = 10 mA Ports 12 to 14 IOL = 1.6 mA IOL = 400 A IOL = 100 A ILIH1 Input leakage current high Input leakage current low Output leakage current high Output leakage current low Internal pull-up resistor (mask option) ILIH2 ILIH3 ILIL1 ILIL2 ILOH1 ILOH2 ILOL VIN = VDD VIV = 6 V VIN = 0 V VOUT = VDD VOUT = 6 V VOUT = 0 V Ports 12 to 14 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0.35 0.35 0.3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V MIN. 0.7 VDD 0.8 VDD 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD 0.8 VDD VDD - 0.5 VDD - 0.3 0 0 0 0 0 VDD - 1.0 VDD - 0.8 VDD - 0.5 VDD - 0.2 0.35 2.0 0.4 0.5 0.3 2.0 1.0 0.4 0.5 0.3 2.0 0.4 0.5 0.3 3 20 15 -3 -20 3 15 -3 10 35 60 TYP. MAX. VDD VDD VDD VDD VDD 6 6 VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.4 0.25 UNIT V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
VIH1 VIH2
Input voltage high
VIH3
Ports 12 to 14
VIH4
X1, X2
Other than below X1, X2 Ports 12 to 14 (open-drain) Other than below X1, X2 Other than below Ports 12 to 14 (open-drain)
A A A A A A A A
k
RL
49
PD75116H,75117H
DC CHARACTERISTICS (Ta = -40 to +60 C, VDD = 1.8 to 5.5 V)
PARAMETER SYMBOL TEST CONDITIONS VDD = 5 V 10 % *2 IDD1 4.19 MHz Crystal oscillation C1 = C2 = 22 pF Supply current*1 IDD2 VDD = 3 V 10 % *2 VDD = 2 V 10 % *3 VDD = 5 V 10 % HALT mode VDD = 3 V 10 % VDD = 2 V 10 % VDD = 5 V 10 % IDD3 STOP mode VDD = 3 V 10 % VDD = 2 V 10 % MIN. TYP. 3.0 1.6 0.6 0.7 280 120 0.2 0.1 0.05 MAX. 9.0 4.8 1.8 2.1 860 360 50 20 10 UNIT mA mA mA mA
A A A A A
* 1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode. 3. When the PCC register is set to 0010 for operation in the low-speed mode. COMPARATOR CHARACTERISTICS (Ta = -10 to +60 C*, VDD = 1.8 to 5.5 V)
PARAMETER Compare accuracy Threshold voltage PTH input voltage Comparator circuit current consumption SYMBOL VACOMP VTH VIPTH VDD = 5.0 V PTHM7 set to "1" VDD = 3.0 V VDD = 2.0 V 0 0 0.7 0.3 0.1 TEST CONDITIONS MIN. TYP. MAX. 100 VDD VDD UNIT mV V V mA mA mA
*
The comparator cannot operate in the range of Ta = -40 to -10 C. It must be used within the range of Ta = -10 to +60 C.
50
PD75116H,75117H
AC CHARACTERISTICS (Ta = -40 to +60 C, VDD = 1.8 to 5.5 V)
PARAMETER CPU clock cycle time* (Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency SYMBOL TEST CONDITIONS VDD = 2.7 to 5.5 V tCY 1.91 VDD = 2.7 to 5.5 V fTI 0 tTIH, tTIL Input VDD = 4.5 to 5.5 V Output SCK cycle time tKCY Input Output Input VDD = 4.5 to 5.5 V SCK high/low-level width tKH, tKL Output Input Output SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK INT0 to INT4 high/low-level width RESET low-level width tSIK tKCY/2 - 50 1.6 tKCY/2 - 150 100 ns 3.2 3.8 0.4 0.95 VDD = 2.7 to 5.5 V 0.48 1.8 0.8 275 kHz 0 16 1 MIN. 0.95 TYP. MAX. 16 UNIT
s s
MHz
TI0, TI1 input high/ low-level width
s s s s s s s
s
ns ns
tKSI VDD = 4.5 to 5.5 V tKSO
400 0 0 300 1000
ns ns ns
tINTH, tINTL tRSL
5
s s
5
51
PD75116H,75117H
*
The CPU clock () cycle time is determined by the oscillator frequency of the connected resonator and the setting of the processor clock control register (PCC). The graph on the right shows the characteristic for cycle time tCY supply current VDD during system clock operation.
tCY vs. VDD
100
10
Cycle Time tCY [ s]
Operating Guarantee Range
1.0
0.1 0 1 2 3 4 5 6 7
Supply Voltage VDD [V]
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET) (1) VDD = 2.7 to 5.5 V
0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD
Test Points
(2)
VDD = 1.8 to 2.7 V
0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD
Test Points
52
PD75116H,75117H
Clock Timing (1) VDD = 2.7 to 5.5 V
1/fX tXL tXH
X1 Input
VDD - 0.5 V 0.4 V
(2)
VDD = 1.8 to 2.7 V
1/fX tXL tXH
X1 Input
VDD - 0.3 V 0.25 V
TI0,TI1 Input Timing
1/fTI tTIL tTIH
TI0, TI1
0.8 VDD 0.2 VDD
53
PD75116H,75117H
Serial Transfer Timing
tKCY tKL tKH
SCK
0.8 VDD 0.2 VDD
tSIK
tKSI
SI
Input Data
0.8 VDD 0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
INT0-INT4
0.8 VDD 0.2 VDD
RESET Input Timing
tRSL
RESET
0.2 VDD
54
PD75116H,75117H
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +60 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal set time Oscillation stabilization wait time*2 SYMBOL VDDDR IDDDR tSREL Release by RESET tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fXX TEST CONDITIONS MIN. 1.8 0.05 TYP. MAX. 5.5 10 UNIT V
A s
ms
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable operation when oscillation is started. 3. Depends on the basic interval timer mode register (BTM) setting (see table below).
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT TIME (Figures in parentheses are for operation at fXX = 4.19 MHz) 220/fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
55
PD75116H,75117H
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
56
PD75116H,75117H
13. PACKAGE INFORMATION
64-PIN PLASTIC QFP ( 14)
64 PIN PLASTIC QFP ( 14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15 +0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
55
Q
57
PD75116H,75117H
5
64-PIN PLASTIC QFP ( 12)
64 PIN PLASTIC QFP ( 12)
A B
48 49
33 32
detail of lead end
C
D
S
64
F
1
17 16
G
P
H
IM
J K
N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
L P64GK-65-8A8 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 14.8 0.4 12.0 0.2 12.0 0.2 14.8 0.4 1.125 1.125 0.30 0.10 0.13 0.65 (T.P.) 1.4 0.2 0.6 0.2 0.15+0.10 -0.05 0.10 1.4 0.1 0.1 1.7 MAX. INCHES 0.583 0.016 0.472+0.009 -0.008 0.472+0.009 -0.008 0.583 0.016 0.044 0.044 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.055 0.008 0.024+0.008 -0.009 0.006+0.004 -0.003 0.004 0.055 0.004 0.004 0.067 MAX.
58
M
55
Q
PD75116H,75117H
14. RECOMMENDED SOLDERING CONDITIONS
The PD75117H should be soldered and mounted under the conditions recommended in the table below. For details of recommended conditions, refer to the information document "Semiconductor Device Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 14-1 Surface Mount Type Soldering Conditions (1)
5
PD75117HGC: 64-Pin Plastic QFP ( 14 mm)
Soldering Conditions Package peak temperature : 230 C, Duration : 30 sec. max. (at 210 C or avove), Number of times : twice Flux washing by the water after the first reflow should be avoided. Package peak temperature : 215 C, Duration : 40 sec. max. (at 200 C or above), Number of times : twice Flux washing by the water after the first reflow should be avoided. Solder bath temperature : 260 C max., Duration : 10 sec. max., Number of times : once, Preheating temperature : 120 C max. (package surface temperature) Pin part temperature : 300 C max., Duration : 3 sec. max. (per device side) Recommended Condition Symbol
Soldering Method
Infrared reflow
IR30-00-2
VPS
VP15-00-2
Wave soldering
WX60-00-1
Pin part heating
--
(2)
PD75117GK: 64-Pin Plastic QFP ( 12 mm)
Soldering Conditions Package peak temperature : 230 C, Duration : 30 sec. max. (at 210 C or avove), Number of times : twice, Time limit: 7 days* (thereafter 10 hours prebaking at 125 C required) Flux washing by the water after the first reflow should be avoided. Package peak temperature : 215 C, Duration : 40 sec. max. (at 200 C or above), Number of times : twice, Time limit: 7 days* (thereafter 10 hours prebaking at 125 C required) Flux washing by the water after the first reflow should be avoided. Pin part temperature : 300 C max., Duration : 3 sec. max. (per device side) Recommended Condition Symbol
Soldering Method
Infrared reflow
IR35-107-2
VPS
VP15-107-2
Pin part heating
--
*
For the storage period after dry-pack decupsulation storage conditions are max. 25 C, 65 % RH. Use of more than one soldering method should be avoided (except in the case of pin part heating).
Note
59
PD75116H,75117H
5
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD751xx SERIES PRODUCTS
Product Name Item ROM (byte) RAM (x 4 bits) Instruction set Total CMOS input CMOS input/output I/O N-ch open-drain port input/output Withstand voltage Pull-up resistor Analog input Power-on reset circuit On-chip (Mask option) Power-on flag Operating voltage Operating temperature range Minimum instruction execution time 2.7 to 6.0 V -40 to +85 C 0.95 s (operating at 4.5 to 6.0 V) 3.8 s (operating at 2.7 V) 2.7 to 5.0 V (Ta = -40 to +50 C) 2.8 to 5.0 V -40 to +60 C 0.95 s (operating at 4.5 to 5.0 V) 1.91 s (operating at 2.7V) None 10 32 (LED direct drive capability *2)
PD75104/106/108/112/116
4K/6K/8K/12K/16K (Mask ROM) 320/320/512/512/512
PD75104A/108A
4K/8K (Mask ROM) 320/512 75X High-End 58 10 (Pull-up resistor mask option : 4)
PD75108F/112F/116F
8K/12K/16K (Mask ROM) 512
10
32 (Pull-up resistor mask option : 24, 32 (LED direct drive capability *2) LED direct drive capability) 12 (LED direct drive capability *2)
+12 V Can be incorporated by mask option 4 (4-bit precision)
+10 V
Package
* 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
* 64-pin plastic QFP ( 14 mm) (Resin thick 2.55 mm) * 64-pin plastic QFP ( 14 mm) (Resin thick 1.5 mm)
* 64-pin plastic QFP (14 x 20 mm)
*
1. 75X High-End can also be used by means of the 16K-byte mode/24K-byte mode switching function. 2. For details, refer to the electrical specifications in each data sheet.
60
PD75116H,75117H
PD75116H/117H
16K/24K (Mask ROM) 768 75X High-End/Extended High-End
PD75P108B
8K (One-time PROM, EPROM) 512 75X High-End 58 10
PD75P116
8K (One-time PROM)
PD75P117H
24K (One-time PROM) 768 75X Extended High-End*1
32 (LED direct drive capability *2) 12 (LED direct drive capability *2) +6 V Can be incorporated by mask option 4 (4-bit precision) +12 V None +6 V
None
1.8 to 5.5 V -40 to +60 C 0.95 s (operating at 2.7 V) 1.91 s (operating at 1.8 V) * 64-pin plastic QFP ( 12 mm) * 64-pin plastic QFP ( 14 mm) (Resin thick 2.55 mm)
2.7 to 6.0 V -40 to +85 C
5 V 10 %
1.8 to 5.5 V -40 to +60 C
0.95 s (operating at 4.5 to 6.0 V) 3.8 s (operating at 2.7 V)
0.95 s (operating at 4.75 to 5.5 V)
0.95 s (operating at 2.7 V) 1.91 s (operating at 1.8 V) * 64-pin plastic QFP ( 12 mm) * 64-pin plastic QFP ( 14 mm) (Resin thick 2.55 mm)
* 64-pin plastic shrink DIP (750 mil) * 64-pin ceramic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
* 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
61
PD75116H,75117H
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75116H/75117H.
IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75108AGC-R EV-9200G-64 Hardware EP-75117GK-R EV-9500G-64 PG-1500 PA-75P117GC PA-75P117GK IE control program Software PG-1500 controller RA75X relocatable assembler
75X series in-circuit emulator Emulation board for the IE-75000-R or IE-75001-R Emulation probe for the PD75116HGC/75117HGC. A 64-pin conversion socket (EV9200G-64) is also provided. Emulation probe for the PD75116HGK/75117HGK. A 64-pin conversion socket (EV9500G-64) is also provided. PROM programmer PROM programmer adapter for the PD75P117HGC, connected to the PG-1500. PROM programmer adapter for the PD75P117HGK, connected to the PG-1500.
Host machines * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3) * IBM PC/ATTM (PC DOSTM Ver.3.1)
*
1. Maintenance product 2. Not incorporated in the IE-75001-R. 3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software.
62
PD75116H,75117H
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
5
Document Name User's Manual Instruction Application Table 75X Series Selection Guide
Document Number IEM-1340 -- IF-1027
Development Tools Documents
Document Name IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual Hardware EP-75117GK-R User's Manual PG-1500 User's Manual Operation Volume RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Language Volume
Document Number EEU-1455 EEU-1294 EEU-1318 EEU-1335 EEU-1346 EEU-1343 EEU-1291
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guide Guarantee Guide Microcomputer Related Products Guide Other Manufacturers Volume
Document Number IEI-1213 IEI-1207 IEI-1209 -- -- MEI-1202 --
Note
The information in these related documents is subject to change without notice. For design purpose, etc., be sure to use the latest ones.
63
PD75116H,75117H
64
PD75116H,75117H
65
PD75116H,75117H
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.

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